1. Field of the Invention
The present invention relates to a system and an apparatus used when a CPU reads information such as hardware version information and DIP switch settings that specify a test mode when a piece of equipment is started up, and more particularly to an information transmission system and an apparatus for serially transmitting information using one clock signal line and one data signal line.
2. Background of the Invention
General-purpose field programmable gate arrays (FPGAs) have come into common use as programmable logic devices for use in computers and, while these devices feature the advantage that their operation is controllable by the circuit diagram programmed therewithin, these devices also have the problem in that it is difficult to ascertain what circuit version is operating.
For this reason, version management is an important factor when using these devices.
Although version management is commonly done by applying a physical label in the form of a seal on the device, a more reliable method is to embed the version information in the form of a circuit in the device.
It is therefore desirable that the version information be embedded using as simple a circuit and as few signal lines as possible, this applying as well to the passing of DIP switch information used to specify a test mode.
Because the above-noted type of hardware version information and DIP switch information for specifying a test mode need only be read in one time when the hardware is started up, even if the processing for reading the data is complex and requires some time to perform, it is important that the number of signal lines used be small and that this function be implemented with a simple circuit.
In the past, a common method of passing the above-noted type of information to a CPU was that of a parallel connection to a PIO (process input-output).
Another method was that of start-stop synchronized transmission of the information.
In the above-noted method of parallel connection to a PIO, however, although there is the advantage of a simple circuit configuration, there is the accompanying problem of the large number of signal lines that are required.
For example, to pass just 8 bits of information (values from 0 to 255), it is required to use 8 signal lines.
In the above-noted start-stop synchronization method, although it is only necessary to have a single signal line, the passage of even simple information required a complex circuit.
Another method is that of the electronic equipment mode setting apparatus disclosed in the Japanese Unexamined Patent Publication (KOKAI) No. 3-113522.
The above-noted mode setting apparatus has a frequency divider circuit for forming at least 3 different clocks which correspond to at least 3 different operating modes, a mode setting circuit for selecting and outputting 1 of the clocks formed by the frequency dividing circuit, and a discriminating circuit for discriminating which clock is being output by the mode setting circuit, whereby the output of the discriminating circuit is used to detect the operating mode of the equipment, thereby enabling an inexpensive simple configuration to be used in making settings of multiple modes.
The above-noted disclosure, however, does not solve the problem of achieving data transmission with a single clock, a single data line, and a simple circuit.
Accordingly, it is an object of the present invention to solve the above-noted problem, by providing an information transmission system capable of passing information using a simple circuit and few signal lines.